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XE1283
4.2
XE8806A/XE8807A BRIEF DESCRIPTION
The top level block schematic of the circuit is shown in figure below. The heart of the circuit consists of the Coolrisc816
CPU (central processing unit) core. This core includes an 8x8 multiplier and 16 internal registers.
The bus controller generates all control signals for access to all data registers other than the CPU internal registers.
The reset block generates the adequate reset signals for the rest of the circuit as a function of the set-up contained in its
control registers. Possible reset sources are the power-on-reset (POR), the external pin NRESET, the watchdog (WD), a
bus error detected by the bus controller or a programmable pattern on Port A.
The clock generation and power management block sets up the clock signals and generates internal supplies for different
blocks. The clock can be generated from the RC oscillator (this is the start-up condition), the crystal oscillator (XTAL) or
an external clock source (given on the XIN pin).
The test controller generates all set-up signals for different test modes. In normal operation, it is used as a set of 8 low
power RAM. If power consumption is important for the application, the variables that need to be accessed frequently
should be stored in these registers rather than in the RAM.
The IRQ handler routes the interrupt signals of the different peripherals to the IRQ inputs of the CPU core. It allows
masking of the interrupt sources and it flags which interrupt source is active.
Events are generally used to restart the processor after a HALT period without jumping to a specified address, i.e. the
program execution resumes with the instruction following the HALT instruction. The EVN handler routes the event signals
of the different peripherals to the EVN inputs of the CPU core. It allows masking of the event sources and it flags which
event source is active.
The instruction memory is a 22-bit wide flash memory. The maximal number of instructions in XE8806A mode
(FLASH_FR=’1’) is 8192 while in XE8807A mode (FLASH_FR=’0’) it is 4096.
The data memory on this product is a 512 byte SRAM.
Port A is an 8 bit parallel input port. It can also generate interrupts, events or a reset. It can be used to input external
clocks for the timer/counter/PWM block.
Port B is an 8 bit parallel IO port with analog capabilities. The USRT, UART, PWM and CMPD blocks also make use of
this port.
Port D is originally a general purpose 8 bit parallel I/O port used in the XE1283 for the API bus.
The USRT (universal synchronous receiver/transmitter) contains some simple hardware functions in order to simplify the
software implementation of a synchronous serial link.
The UART (universal asynchronous receiver/transmitter) contains a full hardware implementation of the asynchronous
serial link.
The RFIF interface (or BitJockey? ) is a serial interface dedicated to communication with RF circuits and more
specifically with the XE1203 in the XE1283. From the CPU side, it very much looks like an ordinary UART but it also
implements low level coding/decoding and frame synchronization. The input/output pins are multiplexed on port D.
The counters/timers/PWM can take their clocks from internal or external sources (on Port A) and can generate interrupts
or events. The PWM is output on Port B.
The VLD (voltage level detector) detects the battery end of life with respect to a programmable threshold.
? Semtech 2005
15
www.semtech.com
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